| 摘要 |
PURPOSE:To reduce the time of frame synchronization establishment and to prevent a malfunction at asynchronizing state by modulating logic between a frame pulse and a data by a prescribed pulse code and sending the result, allowing a reception sectin to generate an identification clock and a discrimination clock and recovering a paralleled data after the frame pulse is detected. CONSTITUTION:A modulation circuit 3 in a transmission section A modulates a frame pulse (f) and a serial data (g) from a transmission timing generator 1 into pulse codes of '1100' and pulse codes of '1100', '1000' respectively for logic 1, 0 the data (g) by using clocks (a), (b) and sends a transmission data (h). A reception section C consists of a clock recovery circuit 4 generating the identification clock (i) and the discrimination clock (j) phase-locked to the transmission data (h), a serial/parallel converter 5 generating parallel codes K1-K4, a frame detector 6, a data detector 7, a serial/parallel converter 8 outputting outputs Q1-Qn from a serial data (m) and a hold circuit 9 recovering parallel data D'1-D'n. Thus, the detection time of the frame pulse is reduced by applying sampling at all time slot locations of the pulse code of the transmission data (h) and the parallel data is recovered after the frame pulse is detected, then the operation at asynchronization is made stable.
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