发明名称 MEMORY ACCESS CONTROL PROCESSING SYSTEM
摘要 PURPOSE:To control the start of a system with the small number of times of access starting by controlling the start of an access unit to be accessed when any one of plural access units is being used, and then controlling the start of remaining access units. CONSTITUTION:When a memory controller 2 is started so as to access a memory device 1, the starting is controlled so that the device 2 simultaneously accesses plural requested access units, or if any one of the plural requested access units is busy, reads out busy information in an access enabled status control part 2-1 to inhibit the control of access start. When there is no busy access unit, an MSU starting part 2-6 controls the device 2 on the basis of informations from address comparing parts 2-4, 2-5 so that the device 2 is to access the device 1 at every access unit or at every pair of access units.
申请公布号 JPS61286943(A) 申请公布日期 1986.12.17
申请号 JP19850128924 申请日期 1985.06.13
申请人 FUJITSU LTD 发明人 NAGASAWA SHIGERU
分类号 G06F12/06;G06F12/00 主分类号 G06F12/06
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