Dynamic memory with intermediate column derode

摘要

A dynamic read/write memory array has a column decode and data input/output arrangement constructed to compensate for large capacitive loads in the I/O circuitry. In a first stage, a buffer is employed between sense amplifiers and segmented intermediate I/O lines. Each segment is a small fraction of the I/O load. First-level column decoding selects one column for each segment. A second level of column decoding employs tri-state buffers which can only be activated during a read with the proper column address. When writing, all buffers are in the high impedance state for reading while the selected buffer is written into through decoded pass gates.