发明名称 |
MULTI-MODE SET ASSOCIATIVE CACHE MEMORY DYNAMICALLY CONFIGURABLE TO SELECTIVELY ALLOCATE INTO ALL OR A SUBSET OF ITS WAYS DEPENDING ON THE MODE |
摘要 |
A cache stores 2̂J-byte cache lines has an array of 2̂N sets each holds tags each X bits and 2̂W ways. An input receives a Q-bit address, MA[(Q−1):0], having a tag MA[(Q−1):(Q−X)] and index MA[(Q−X−1):J]. Q is at least (N+J+X−1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2̂W ways of the selected set when operating in a first mode; and into a subset of the 2̂W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion. |
申请公布号 |
EP3055774(A1) |
申请公布日期 |
2016.08.17 |
申请号 |
EP20140891602 |
申请日期 |
2014.12.14 |
申请人 |
VIA ALLIANCE SEMICONDUCTOR CO., LTD. |
发明人 |
REED, DOUGLAS, R. |
分类号 |
G06F12/08;G06F12/0864;G06F12/123;G06F12/128 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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