发明名称 CMOS TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To prevent a latch-up phenomenon effectively, by providing a surge- current limiting resistor between an external power source terminal and an internal power source terminal, which supplies power to a central circuit part. CONSTITUTION:A surge-current limiting resistor 9 is formed with poly silicon so as to have the resistance value of 200OMEGA. The current consumption in a central circuit part 5 is 0.5mA at the operating frequency of 500KHz. Therefore the DC voltage drop in the surge-current limiting resistor 9 is about 0.1V, which is a level where signal transmission between input and output buffers 6 and 7 is not blocked. With respect to the AC voltage drop, the parasitic capacitance of about 1,000pF owing to a P well is present between internal power source terminals 81 and 82. The parasitic capacitance smoothes the AC. The surge current from the power source is decreased to the level, where the current does not become the triggering current of a parasitic thyristor, by the surge- current limiting resistor.
申请公布号 JPS61285751(A) 申请公布日期 1986.12.16
申请号 JP19850127621 申请日期 1985.06.12
申请人 NIPPON DENSO CO LTD 发明人 KATO MITSUHARU;SENBOKUYA KOJI
分类号 H01L27/04;H01L21/822;H01L27/06;H01L27/08 主分类号 H01L27/04
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