| 摘要 |
<p>PURPOSE:To reduce the generation of glitch by selecting a designated clock in response to the control signal which designates one of plural clocks and the feedback output clock. CONSTITUTION:If the clock delivered presently as an output clock phiOUT is equal to the 1st clock phi1, the control signal (l) is changed to a low level from a high level to switch the 2nd control signal. Thus the 2nd flip-flop FF2 is reset by the change of the signal (l) and synchronously with the fall of the clock phi1. Then the 3rd flip-flop FF3 becomes enable and is set synchronously with the next fall of the 2nd clock phi2. The clock phiOUT is toothless in a switching mode owing to a series of said actions and changed into the clock phi2. Thus no glitch is produced.</p> |
