| 摘要 |
PURPOSE:To obtain a structure for a memory cell optimized for a large capacity memories, by providing a slant surface at the upper part of a groove, forming one transistor on the slant surface, forming one capacitor in the groove, thereby reducing the substantial plane area of the memory cell. CONSTITUTION:In a P-type semiconductor substrate 1, many trapezoidal mesa parts 3, which are divided into a grid shape by grooves 2, are formed. At the center of each mesa part 3, an N<+> type diffused layer 4 is provided. A slant surface 5 is formed at the peripheral part of the mesa part 3 to the groove 2. An N<+> type diffused layer 6 is provided on the side surface of the groove 2. A field oxide film 7 is provided at the bottom surface of the groove 2. A P<+> type channel stopper region 8 is provided directly beneath the film 7. A gate electrode 10 comprising polysilicon is provided on the slant surface 5. One transistor is formed jointly by both diffused layers 4 and 6. In the groove 2, a capacitor electrode 11 comprising polysilicon is provided on the N<+> type diffused layer 6 through the insulating film 9. One capacitor is formed by the electrode 11 and the N<+> diffused layer 6 on the side surface of the groove 2. The polysilicon of the gate electrode 10 is extended and word lines 12 are formed. Bit lines 13 comprising aluminum shown by an alternate long and short dash lines are connected to the N<+> type diffused layer 4. |
