| 摘要 |
PURPOSE:To cope with a high speed conversion of a dynamic memory by executing in parallel a precharge, and an input of address information corresponding to the next memory cycle. CONSTITUTION:A timing generator 30 is constituted of the first timing generator 30a and the second timing generator 30b. In case when a row address strobe signal and a column address strobe signal are the first clock, the second timing generator 30b generates the second clock which has been delayed from its first clock, based on this first clock. The delay time extends a precharge time of a memory cycle by delaying the second row address strobe signal, and makes its precharge and an address input corresponding to the next memory cycle overlap each other. By this parallel processing time portion, a repeated period of the memory cycle can be made shorter than before.
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