| 摘要 |
<p>PURPOSE:To relax the restriction of an IC depending on external limit conditions by constituting the titled circuit with plural input terminals, plural delay circuits having different delay times, a logic element and a flip-flop. CONSTITUTION:A clock signal fed externally to one input terminal selected in advance in matching withy an external condition among clock input terminals CL0-CLM is provided respectively with a different delay time from the terminals CL0-CLM to which clock signals are given and the result is inputted to a logic element 2. Delay circuits 10, 20, 21-M0, MN having respectively the same delay time T and the delay time from each input terminal is set as 0, T...NT. The element 2 is a OR circuit and its output is fed to the FF1. In this case, only the desired clock signal is fed to the FF1. A data signal is set externally to a data input terminal DI of the FF1 in response to a clock signal fed from the element 2 and an output is given at a data output terminal DO.</p> |
