| 摘要 |
PURPOSE:To improve the debugging efficiency of programs in a multi-CPU constitution by controlling CPUs so that all CPUs are interrupted when break occurs in at least one CPU. CONSTITUTION:When a command is inputted, an instruction 5 is saved and is substituted with a PI instruction, and CPUs A and B execute the program alternately in time division while being switched to each other at every instruction. When the CPU A is requested to execute the PI instruction, a PI instruction detecting means 3 detects it to output a PI instruction detection signal. Since a flag 100 is set at this time, all PI request means 4 are activated. Consequently, the CPU B performs the interruption processing immediately when the CPU A is switched to the CPU B after executing the PI instruction. The control of both CPUs is transferred to a monitor program at the next CPU switching time.
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