| 摘要 |
PURPOSE:To supply a resetting circuit for a MOS image forming device array with a quick action by applying simultaneously a chip resetting signal to all word lines in the MOS image forming array and resetting simultaneously the photocell on all the word lines. CONSTITUTION:At an interlace gate circuit 50, the signal from a vertical shift register arrives at a vertical shift resister line 30, and a line gate 46 is successively made effective to a word line 24. Respective resetting gates 48 are controlled by a LINE RESET signal, and the origin of respective gates 48 are fitted at a CHIP RESET signal. The LINE RESET is synchronized to the vertical shift register and clocked. At the normal action, the CHIP RESET signal is grounded to the low level. Thus, the word line 24 comes to be effective since the line 30 is high and the LINE RESET signal is low or the CHIP RESET signal is high and the LINE RESET signal is high, and for such a reason, in any case, the high level is obtained. To reset wholly the photocell, both RESET signals must be the high level ranging over all cycles of the horizontal shift register, and the time is much smaller than the conventional time.
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