| 摘要 |
PURPOSE:To facilitate the return of phase comparing output to an origin even when a phase is largely shifted by the effect due to disturbance and to prevent a lead-in time, by applying limiter to phase comparing output to hold said output within a specific difference range. CONSTITUTION:The phases of binary input signal respectively emitted from terminals 1, 2 are compared by a subtraction circuit 5 formed of a complement circuit 3 and an adder circuit 4. When this phase comparing output is a set value or more, a comparing circuit 6 outputs a control signal to control a change-over circuit 6 along with the direction output corresponding to the polarity from a direction detecting circuit 7. By this method, the phase comparing output equal to or less than the set value is outputted from the circuit 8 as it is and, when the phase comparing output is the set value or more, limiter is applied to the phase comparing output to output the constant phase comparing output held within a specific phase difference range. Therefore, even when a phase comparator received large effect due to disturbance such as the abrupt change of frequency, the phase comparing output comes to a single positive or negative component and the return of the phase comparing output to an origin becomes easy. As a result, a lead-in time becomes short and a digital phase comparator capable of being used in PLL is obtained. |
