| 摘要 |
PURPOSE:To prevent a latch-up by forming each MOSFET for a CMOS by the same processes as a second conduction type buried diffusion layer and a color layer for a bipolar transistor and connecting several MOSFET by a second conduction type channel stopper layer. CONSTITUTION:Three N<+> buried layers 2 are formed to one parts on a P-type Si substrate 1, an N<-> epitaxial layer 3 is grown, and a P<-> well layer 5 is shaped to an N channel MOSFET section through ion implantation. N<+> channel stopper diffusion layers 17 are formed by the same process as the formation of an N<+> color diffusion layer 6 to a bipolar section, and N<+> source/drain diffusion layers 9 are shaped into the P<-> well layer 5 in the N channel MOSFET section and P<+> source/drain diffusion layers 10 into the epitaxial layer 3 in a P channel MOSFET section. Gate electrodes 14 are formed onto insulating films 15 among respective source/drain for a CMOS section while source/drain electrodes 16 are shaped respectively to the sources/drains 9, 10. Accordingly, a latch-up is prevented without increasing the number of processes. |
