发明名称 DATA BUFFER CONTROL SYSTEM
摘要 PURPOSE:To improve the using efficiency of a main memory and to facilitate a data transfer control by providing a comparing means comparing the contents of a table with those of a register and transferring reception data to the buffer in an optimum size selected by said means. CONSTITUTION:A control circuit 4 stores sizes and addresses of buffers in different sizes, which are previously allocated to the main memory, on the table 6 and the reception data length in the register 5. A comparator circuit 7 reads sizes in increasing order and compares them with the data length in the register 5. When the size longer than the data length is detected, the circuit 7 causes a register 8 to store the address when the longer size is detected. Accordingly, among buffers in different sizes, which are stored on the table 6, the buffer having the larger than the transferred data length and the minimum size is selected. Here the circuit 4 transfers data to the buffer at the address specified by the register 8.
申请公布号 JPS61279969(A) 申请公布日期 1986.12.10
申请号 JP19850122008 申请日期 1985.06.05
申请人 FUJITSU LTD 发明人 KAMITATE MORIHIRO;YAMAMOTO NOBORU;IHI TOSHIAKI;MITSUISHI KAZUYUKI
分类号 G06F13/10 主分类号 G06F13/10
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