| 摘要 |
PURPOSE:To prevent a subsequent erroneous processing by detecting that contents in a shift register in case of the contents are shifted before a CPU carries out the prescribed access and causing the CPU to generate an interruption. CONSTITUTION:The shift register 11 inputs and outputs serial data in synchronization with a clock pulse CK, and an n-bit counter 12 counts said clock, detects the shift of the number (n) of bits of one word in the shift register 11, and sets an FF 14. In this state, a programmable counter 13 counts access times to the shift register 11, and resets the FF 14 when the number reaches a set one. Namely when the clock pulse CK falls before the number of access times reaches the set one after one word has been transferred, an over-shift flag 161 is set, and the interruption is applied to the CPU 2.
|
