| 摘要 |
PURPOSE:To obtain a high-speed division device which is suitable for the formation of an LSI by using an addition means having a simple circuit contritution in place of a partial quotient correction means. CONSTITUTION:A divisor Y is supplied to a dividend register 1 and also set to a register 3 after retrieving an approximate reciprocal number T through a reciprocal number table 14. Then a correction number D=Y.T is obtained at a register 6 via a multiplier 8, an adder 9 and a full-adder 10. Then a dividened X is also multiplied by the number T to obtain the 1st temporary partial quotient R1 at the register 6. The integer part and a bit after a decimal point of the quotient R1 are supplied to a partial quotient calculation circuit 11 to obtain the first partial quotient Q1 and the complement -Q1 of 2. The quotient R1 is supplied to a quotient collection adder 12 and a quotient register 7; while the complement -Q1 is supplied to a multiplication register 3. Thus the second temporary partial quotient R2 is obtained at the register 6. In the same way, the second partial quotient Q2 and -Q2 are produced by the circuit 11. This division loop is repeated by (m+1) times to obtain the final temporary partial quotient Rm+1 at the register 6. This quotient Rm+1 is corrected by a quotient correction/detection circuit 13, and the result of this correction is supplied to the register 7. |
