发明名称 SERIAL BUS SYSTEM
摘要 PURPOSE:To improve the reliability and efficiency of transmission by permitting a sub-station to return a confirmation response with respect to a receiving signal and reporting the interruption request of the sub-station. CONSTITUTION:A central station is provided with a computer controlling the central station and a microprocessor muPC communicating through plural interface registers. The muPC also communicates between microprocessors muPSi of respective sub-stations. The muPSi of each sub-station controls its sub-station. Conductors TXD and RXD transfer information transmitted from the central station to the sub-station and that transmitted to the central station from an arbitrary sub-station, respectively. Registers include a STATUS register, a COMMAND register, an ADDRESS register, a WR.DATA register and an RD.DATA register.
申请公布号 JPS61278956(A) 申请公布日期 1986.12.09
申请号 JP19860127121 申请日期 1986.05.30
申请人 YOKOGAWA HEWLETT PACKARD LTD 发明人 JIYUNEBIEEBU EMU BURIIKU;KENTO DABURIYUU RUUMAN
分类号 G06F13/00;G06F13/42 主分类号 G06F13/00
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