发明名称 OUTPUT INTERRUPTING CIRCUIT OF LOGIC CIRCUIT
摘要 PURPOSE:To interrupt an output until a signal output source of various peripheral devices is operated normally by using a one-shot multivibrator triggered based on a reset signal and a clock signal of a microcomputer. CONSTITUTION:The clock signal and the reset signal are ANDed by an AND gate G1 and the resulting signal triggers the one-shot multivibrator MV. The operating time of the vibrator MV is set longer than the longest time of an expected unstable time of various peripheral devices. Since an output signal of the MV is inputted to an ANG gate G2, so long as the MV is operated, the signal output of a signal output source SIG is interrupted. Thus, the output is interrupted until the signal output source of the various peripheral devices is operated normally.
申请公布号 JPS60173923(A) 申请公布日期 1985.09.07
申请号 JP19840029005 申请日期 1984.02.17
申请人 FUJITSU KK 发明人 IGI YOUZOU;ETOU KOUJI
分类号 G06F11/14;G06F11/00;H03K19/00;H03K19/003 主分类号 G06F11/14
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