SIMULATION METHOD FOR ERRORS IN LOGIC CIRCUIT AND CIRCUIT DEVICE,申请号JP19860122065-传众专利搜索

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发明名称	SIMULATION METHOD FOR ERRORS IN LOGIC CIRCUIT AND CIRCUIT DEVICE
摘要
申请公布号	JPS61278946(A)	申请公布日期	1986.12.09
申请号	JP19860122065	申请日期	1986.05.27
申请人	SIEMENS AG	发明人	MIHIAERU BEENAA
分类号	G06F11/25;G06F11/26;G06F17/50	主分类号	G06F11/25
代理机构		代理人
主权项
地址

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