| 摘要 |
PURPOSE:To attain precise failure inspection easily by forming test areas corresponding to the number of memory address lines in which data are to be written, previously recording different prescribed data required for the inspection of failure in these areas respectively, reading out these data successively, and detecting whether respective read data coincide with the previously recorded failure testing data or not. CONSTITUTION:A CPU chip 40 is connected with a PROM41 through e.g. a control line 51, 13 address lines 52 having '0' bits up to 12 bits and 8 data lines 53 having '0' bits up to 7 bits. A reference table 404 for storing the same data as test data stored in test areas in the PROM chip 41 are formed in a ROM402 in the CPU chip 40. In the inspection of failure, addresses are successively applied to the address lines 53 on the basis of a failure inspecting program to read out data from the test area. Whether respective read data coincide with the previously recorded data or not is decided by comparing respective data with the corresponding test data written in the reference table 404 stored in the ROM402. |
