| 摘要 |
PURPOSE:To prevent generation of malfunction at data transfer of transmission and reception FEFOs by applying logical operation based on output ready information of the sending FIFO and input ready information of the reception FIFO. CONSTITUTION:When an OR terminal 310 and an IR terminal 320 go both to logical 1, an S-R latch 350 is set, and when they both go to logical 0, the latch is reset and an output of the latch 350 is fed to a shift-out input 122 of the sending FIFO 100 and a shift-in input 211 of the reception FIFO 200 respectively via an SO terminal 360 and an SI terminal 370. Thus, the hand shake in the data transfer between the transmission FIFO and the reception FIFO 200 is attained surely and malfunction due to wiring capacity due to a long wiring or the delay in the buffer gate is prevented. The generation of malfunction in the data transfer between the transmission FIFO and the reception FIFO is prevented with simple circuit constitution and save data transfer is attained.
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