| 摘要 |
An integrated semiconductor circuit with connection pads (1 to 18) on regions (S) adjacent to end faces of a semiconductor chip for electrically connecting electrical signals and/or potentials is described. For electrically connecting some of these electrical signals and/or potentials, further connection pads (4a, 5a, 13a, 14a) are provided inside an array (R) which contains electrical circuits (SF, PS) and at least one area (F) free of the electrical circuits (SF, PS) in the free area (F) between the regions (S). Depending on the envelope used for the integrated semiconductor circuit, either the standard connection pads (4, 5, 13, 14) or the further connection pads (4a, 5a, 13a, 14a) are used for the signals and/or potentials concerned in making contact. …<IMAGE>… |
