Data processing apparatus for virtual memory system

摘要

A data processing apparatus for a virtual memory system including a logical address register, a real address register, a paged address translation table and an address translation buffer in which a map of a fraction of the paged address translation table is stored columnwise. Upon checking address translatability of a logical address into a real address, a bit of a translation control word contained in the column of the address translation buffer relevant to that logical address indicates whether or not a succeeding logical address is susceptible to the address translation. Necessity to pretest the address translatability of every logical address is obviated. System overhead is considerably reduced.