| 摘要 |
PURPOSE:To improve the using efficiency of a memory element by setting a writing cycle at every type of a signal to write in a common memory and reading either signal by one reading cycle. CONSTITUTION:A processing time assigned to 1 channel is divided into two writing cycles A, B and one reading cycle. In the writing cycle A, a writing address counter 212 is selected by a selector 220, a reading address counter 28 is selected by a selector 221 and a comparison circuit 223 compares the outputs of the selectors 220, 221, and when there is no idle area of the writing in a buffer memory 200, outputs a logic 0. When there is the idle area of the writing in the buffer memory 200, a writing pulse is produced in the buffer memory through an AND gate 209. Also in the writing cycle B, the same writing operation is performed and supplied to the buffer memory 200 as a reading address. Thereby, the using efficiency of the memory can be improved.
|
