发明名称 BUFFER CONTROL SYSTEM FOR DATA CONVERTER
摘要 PURPOSE:To cope with the variance of reception time in a channel device by providing plural data conversion buffers minimumly required for data conversion between a reception register and a transmission register to keep the time loss in a data converter to a minimum. CONSTITUTION:If the data transfer speed in a channel device CH3 is reduced by some causes, buffers 00 and 01 of a data conversion buffer 50 are filled up, and following data sent from an I/O 1 are set successively to buffers 10 and 11 of a data conversion buffer 51 from a reception register 4. During this time, data in buffers 00 and 01 are preferred as data transmitted to the device CH3, and data in buffers 10 and 11 are set to a transmission register 6 and are transmitted to the device CH3 when buffers 00 and 01 are empty. When the transfer speed in the device 3 is restored, buffers are so controlled that the conversion buffer 50 is not used hereafter and buffers 10 and 11 of the conversion buffer 51 are used. Hereafter, the data conversion buffer serving as the center is switched similarly.
申请公布号 JPS61276048(A) 申请公布日期 1986.12.06
申请号 JP19850118029 申请日期 1985.05.31
申请人 FUJITSU LTD 发明人 IBORI MITSUO
分类号 H04L29/06;G06F5/00;G06F5/06;G06F13/12 主分类号 H04L29/06
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