| 摘要 |
PURPOSE:To obtain a high reliable device which can operate stably at a high speed, by forming a vertical NPN transistor and FET in each separated N island on a P-type substrate, a triple diffused vertical transistor in each P well in the islands, and an FET in each P well. CONSTITUTION:On the P-type Si substrate 1 in which P<+> layer are formed between the spaced N<+> buried layers 2 and on the specific N<+> layers 2, the N<-> epitaxial layer 4 is overlapped. Using the oxide film 13 as a mask, the P<+> layer 7b and P<-> layers 8a, 9a are formed so as to oppose the buried layers. The N layers 14 which are formed by implanting ions into the P<-> layers 9a are pushed in, in order to form the N<+> layers 16-20 in the separation layers 7, P wells 8, 9, and N<-> islands 4-6. Next, the P<+> channel stoppers 12, base taking-out layers 21 of the vertical NPN elements Q1, emitter and collector taking-out layers 22, 23 of the triple diffused PNP elements Q1, emitter and collector taking-out layers 22, 23 of the triple diffused PNP element Q2, and source and drain 24, 25 of the FETs Q4 are formed at the same time, and electrodes are mounted to finish the device. In this way, the triple diffused vertical elements Q1 and FETs having a uniform gate threshold voltage can be formed on a chip in the reduced number of processes. |
