| 摘要 |
PURPOSE:To obtain an IC which is able to reset only on making the power on without providing with reset terminals, by forming an island region to which the power voltage is being connected, near a capacitor for suppressing the voltage rise of a specific node, and by discharging promptly the charges left in the capaitor before making the power on. CONSTITUTION:An n<-> epitaxial layer on the p<-> substrate 1 having the n<+> layers 2, 2 buried, is separated by the p<+> layers 4. In the island 3, the p<+> layer 6 is overlapped partially on the p<+> separating layer 4, and the electrode 8 is formed thereon. Moreover, the n<+> layer 5 is overlapped on the p<+> layer 6 and the elec trode 7 (node NA) is formed on the n<+> layer 5. In the island 3', the n<+> layer 10 and the electrode 9 are formed, being connected to the power voltage VCC, and in an island not shwon in the figure, a system including the negative gates G1-G4, an FF and a latch is consrituted. When the VCC is lowered using the constant-current source Id, the transverse npn transistor Q$5 between the capaci tor C1, VCC and p<-> Si substrate 1 is made on, discharging promptly the charges left in the C1 through the VCC. Accordingly, the time waiting till making the power-on can be shortened.
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