| 摘要 |
PURPOSE:To simplify the logic detecting the fluctuation of a clock signal period by using a ternary/binary counter circuit as a counter circuit so as to use a tri-state value as a value in use. CONSTITUTION:The ternary/binary counter 7 to which a clock signal is inputted via a signal line 1 counts the clock signal and outputs a count C to a latch circuit 4. The circuit 4 latches the value C at the input of sampling signal and outputs a value Ct at a time tn to a latch circuit 5 and an up-down detection circuit 8. On the other hand, the value C latched in the circuit 4 is inputted to the circuit 5, a value Cn-1 is latched at the input of a sampling pulse at a time tn-1 and outputted to the circuit 8. The circuit 8 compares the values Cn and Cn-1 and increments/decrements are count of the counter 7 when the clock signal period is deviated and outputs an up or a down count signal. Thus, the phase fluctuation of the clock signal is detected. |
