发明名称 FULL ADDER
摘要 PURPOSE:To secure a wide action voltage margin with a simple circuit by connecting additionally an FET, which is turned on by the inverting signal of one side input signal of exclusive 'or' and 'not' circuits, between an input terminal and an output terminal. CONSTITUTION:Between the input terminal 11 or 12 of the exclusive 'or' and 'not' circuit 6 of respective exclusive OR circuit and an output terminal 10, respective P channels FET 21 and 22 are applied, and the inverting signal of the input signal of the terminal 11 or 12 is given to respective gates. In the constitution, when two input signals are both 1 level, N channels FET 8 and 9 come to be the ON condition and simultaneously, the FET 21 and 22 are also turned ON in which a 0 level to occur as the inverting signal of one side input signal without fail is given to the gate. Thus, since 1 level input appears through the FET 21 and 22 in parallel through the FET 8 and 9 at the terminal 10, 1 signal having the sufficient level can be obtained without being influenced by the threshold voltage of the FET 8 and 9.
申请公布号 JPS61276024(A) 申请公布日期 1986.12.06
申请号 JP19850118106 申请日期 1985.05.31
申请人 TOSHIBA CORP 发明人 IWAMURA ATSUSHI
分类号 G06F7/50;G06F7/501;G06F7/506 主分类号 G06F7/50
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