| 摘要 |
PURPOSE:To prevent exchanged data from extending over two frames by selectively outputting output of data arrangement obtained by specific change of time slot data by two sets of time division/space division switches and composing them. CONSTITUTION:Each of data D1, D2... delayed by one frame passed through original data of one frame d1, d2..., delay circuits 2-1-2-4 are supplied to switch 1 and switch 3 of time division/space division switch having incorporated memory that makes read modify and write cycle operation. Data other than the first and second bits changed by change of time slot data and output selection are outputted to data D3, D4..., and one frame data of arrangement in which the first bit is delayed data D2 are outputted from the switch 2. Similarly, one frame data in which the second bit is interchanged with delayed data D is outputted from the switch 3. These outputs are composed by wired OR, and exchanged data do not extend over two frames.
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