| 摘要 |
PURPOSE:To speed up the operation of a RAM by making connections with an array of memory cells by a couple of bit lines so that an information signal contained in a selected memory cell is detected. CONSTITUTION:When a control terminal RE varies in level to 'H', contacts N1 and N2 are still at the same potential because corresponding MOS transistors (TR) are equal in gm. When a bit line BL begins to fall to 'L' from said state, the resistance of an nMOST Q1 increases to reduce a current flowing through a pMOST Q6 whose voltage drop becomes small, so that the potential at the node N1 rises. When the potential at the node N1 rises, the resistance of an nMOST Q8 decreases to lower the potential at the node N2, and then the resistance of the pMOST Q6 decreases, so that the potential at the node N1 further rises. This operation starts when the potential of one of bit lines BL and -BL drops to generate a potential difference between the bit lines BL and -BL. Consequently, a readout speed is increased while the power consumption of a CMOS-RAM when it is not in operation is suppressed. |
