| 摘要 |
<p>Method for fabricating field effect transistors of very small size. The grid electrode (20) is comprised of a first metal silicide layer; isolating fillings (30) are formed along side edges of the grid; then, a second metal silicide layer (32) is deposited to form the source and drain electrodes; the region where the second layer covers the first layer, a planing by planarizing engraving is effected so as to obtain a structure of planar electrodes wherein the grid is separated from the source and drain electrodes by an interval which is smaller than that which would enable a separation by photoengraving.</p> |
