发明名称 CONTROL SYSTEM IN FALSE FULL DUPLEX COMMUNICATION MODE
摘要 PURPOSE:To make it possible to omit a circuit for a full duplex communication by processing as if the full duplex communication is performed, by appearance, by a processor built in a terminal equipment. CONSTITUTION:A start bit is detected at a receiving part 8 in a terminal equipment 2 and also, when a data is in transmission at a transmission part 7, a line RD is fixed as a logic '1' by a framing error generating process function 11 and the data to be transmitted is buffered on a buffer 10. And with completing a receiving on a line SD, the fixing of the logic '1' of the line RD is cancelled and the transmission of the data to be transmitted including the content of the buffer 10 is restarted. By this reason, it seems that the full duplex communication is actually being performed judging from the stand point of a key operator.
申请公布号 JPS61274453(A) 申请公布日期 1986.12.04
申请号 JP19850096434 申请日期 1985.05.07
申请人 PANAFACOM LTD 发明人 ABIKO HIROYUKI;ARAKI TSUTOMU;OGAWA SHINJI
分类号 H04L29/08;G06F11/00;G06F13/00;H04L5/14;H04L13/00 主分类号 H04L29/08
代理机构 代理人
主权项
地址