发明名称 CLOCK SYNCRONIZING CIRCUIT
摘要 A clock synchronizing circuit separates and filters a clock component from a digital input wave. The output of the circuit is sampled to produce a two-level signal. A voltage controlled oscillator generates a clock signal having a phase and a frequency which is controlled responsive to the two-level signal.
申请公布号 AU5794386(A) 申请公布日期 1986.12.04
申请号 AU19860057943 申请日期 1986.05.27
申请人 NEC CORP. 发明人 YASUHARU YOSHIDA
分类号 H03L7/00;H03K5/00;H04L7/027;H04L7/033;H04L27/00 主分类号 H03L7/00
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