| 摘要 |
PURPOSE:To improve characteristics of a J-FET such as an operation speed and a mutual conductance by introducing an impurity into the gate control layer of the gate side of a P-N junction by atomic plane doping. CONSTITUTION:On the (100) surface of a semi-insulating GaAs substrate 11, a non-doped GaAs buffer layer 12, an N-type channel layer 13, a plane 14 of Be atomic doping and a non-doped GaAs layer 15 are successively formed by MBE method. Mesa etching is carried out for separation between elements and a gate electrode 16 which has ohmic contact with the GaAs layer 15 is formed on the layer 15. Si ions are implanted by utilizing the gate electrode 16 as a mask and N<+> type contact regions 17 are formed by a heat treatment with a halogen lamp or the like. Source and drain electrodes 18 which have ohmic contact with the regions 17 are formed with gold-germanium/gold (AuGe/ Au). |
