发明名称 LOGICAL SIMULATOR
摘要 PURPOSE:To simulate a filmed pseudo circuit at a high speed by reading out the inter-gate connection data corresponding to the type data on the block as well as the gate type data and performing simultaneously the simulation of the gates constituting the block. CONSTITUTION:A block type storing memory 106 stores the type data on the blocks consisting of the gates for each execution of simulation. A gate connection memory 105 stores the inter-gate connection data on plural gates within a block. An intermediate logic value storing memory 104 stores the state of an input pin of the block and the state of the gate under simulation. Furthermore an arithmetic circuit 108 for plural gates performs simultaneously the simulation of plural gates read out at a time. Thus the inter-gate connection data corresponding to the type data on the blocks and the gate type data are read out in the prescribed order against a test pattern. Then each component gate for blocks is simulated.
申请公布号 JPS61273641(A) 申请公布日期 1986.12.03
申请号 JP19850117129 申请日期 1985.05.30
申请人 NEC CORP 发明人 TAKASAKI SHIGERU
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
代理机构 代理人
主权项
地址