发明名称 LOGICAL SIMULATOR
摘要 <p>PURPOSE:To simulate a filmed pseudo circuit at a high speed by reading out the inter-gate connection data corresponding to the type data on the block to be simulated as well as the gate type data for simulation of each component of the block. CONSTITUTION:Plural block type storing circuits 103 sort and store the type data on plural blocks, and the gate connection circuits 105 corresponding to the circuits 103 store plural inter-gate connection data. Then the gate type storing circuits 106 store plural gate types in response to the circuits 105. Furthermore the arithmetic circuits 108 execute simultaneously the simulation of the gates of plural blocks. Thus the gate type data corresponding to the type data on the blocks to be simulated are read out according to the order desided previously to the test pattern data. Then the gates constituting the blocks are simulated.</p>
申请公布号 JPS61273640(A) 申请公布日期 1986.12.03
申请号 JP19850117128 申请日期 1985.05.30
申请人 NEC CORP 发明人 TAKASAKI SHIGERU
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
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