| 摘要 |
PURPOSE:To reduce the areas of cells, and to improve the degree of integration by each forming floating gates for adjacent memory cells through different manufacturing processes. CONSTITUTION:A mask material is shaped in an element region in a P-type silicon substrate 21, and a field oxide film 22 is formed. The mask material is peeled, gate insulating films 23a, 23b are shaped, a polycrystalline silicon layer 24 is formed onto the whole surface, and a first resist pattern 25 for shaping a first floating gate is formed onto the layer 24. The polycrystalline silicon layer 24 is removed selectively through etching while using the pattern 25 as a mask, thus shaping a first floating gate 26a consisting of polycrystalline silicon. The pattern 25 is peeled, a polycrystalline silicon layer 27 is formed onto the whole surface, and a second resist pattern 28 is shaped and a second floating gate 26b is formed. An oxide film 29 is shaped onto the whole surface, and a control gate 30 controlling the potential of the floating gate is formed. |
