| 摘要 |
PURPOSE:To obtain a circuit obtaining a clock signal with less jitter without using a limiter circuit and realized economically with a small circuit scale by applying a narrow band filtering to an output being nonlinear control of an input signal and controlling a voltage controlled oscillation means with an output being the sampled output of the filter output. CONSTITUTION:A clock component is outputted from the tank circuit 204 of a clock synchronous circuit 21. The output is adjusted for a DC voltage by using a bias voltage Vb, sampled by a clock signal C2 at a flip-flop 211 and when the sampling value is larger than the threshold value of flip-flop 211, the output at an output terminal Q goes to 1 and when smaller, the output goes to 0. When the input at the input terminal D changes to the states (a-c), the output of the output terminal Q shows the phase comparison characteristic representing the relation of phase between the input at the input terminal D and the clock signal C2. Thus, the signal is used as the control signal of the voltage controlled oscillator 208 via a low pass filter 207, then the clock synchronous circuit 21 acts normally like the clock synchronus circuit. |
