发明名称 WRITE DATA COMPENSATING CIRCUIT IN MAGNETIC RECORDER
摘要 <p>WRITE DATA COMPENSATING CIRCUIT IN MAGNETIC RECORDER A write data compensating circuit in a magnetic recorder comprising a shifting circuit for shifting binary data in time series and producing front, present, and rear signals regarding the binary data, and a combination logic circuit for effecting a preshift to the present signal provided as write data in accordance with a pattern of the front, present, and rear signals. The combination logic circuit is comprised of a first circuit operative to discriminate a pitch of each two adjacent inversions of magnetization to be created by the write data and a second circuit operative to adjust each pulse width of the write data based on an analysis by the first circuit.</p>
申请公布号 CA1214870(A) 申请公布日期 1986.12.02
申请号 CA19830440424 申请日期 1983.11.04
申请人 FUJITSU LIMITED 发明人
分类号 G11B5/09;G11B20/10 主分类号 G11B5/09
代理机构 代理人
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