| 摘要 |
PURPOSE:To attain high-speed operation and low power consumption by latching read data via a sense amplifier intermitted to a bit line to disconnect the connection between the sense amplifier and a latch circuit thereby decreasing the logical amplitude of the bit line. CONSTITUTION:When gates T11, T12 are turned on by a word line X11 only at read required period, data of a memory cell M is read by the sense amplifier S1 via gates T15, T16 in the ON state by using a control signal CK11 via bit lines B, B' precharged. When the read required period elapses and the gates T15, T16 are turned off tentatively, the circuit S1 applies amplification without affecting the capacity of the lines B, B' in response to a control signal approx.=21, and its output is latched by a latch circuit LAT, the circuit S1 and the latch LAT are disconnected via gates T15, T16 are turned off and the circuit S1 is precharged when the gates T15, T16 are turned on. Thus, minimized logical amplitude, reduction in the operating period of the sense amplifier and parallel operation of precharing the bit lines and the sense amplifier are attained and high-speed operation/power consumption reduction are attained. |
