发明名称 BIT SYNCHRONIZING DEVICE IN N VERSUS N LOOP
摘要 <p>PURPOSE:To execute the loop transmission without a master station by fetching a clock from the information from a higher order station, correcting the frequency error with the clock of its own station and sending the information with the clock timing of its own station to a lower order station. CONSTITUTION:A signal S1 from the higher order station is inputted to a shift register 2A, a clock signal C1 is detected by a clock generating circuit 1 and inputted to the shift register 2A and a frequency comparing circuit 4. A clock C2 generated at a transmitting clock generating circuit 3 is inputted to the comparing circuit 4. The comparing circuit 4 always compares clocks C1 and C2, changes over the output tap of the shift register 2A by the difference and synchronizes with the clocks C1 and C2. By the synchronized clock C2, an information signal S5 from a transmitting data sending circuit 5 is sent to the lower order station. Thus, when the sending clock is synchronized with the clock from the higher order station once, the N verous N loop transmission can be efficiently executed without the master station regardless of the changing of the transmitting station.</p>
申请公布号 JPS61270937(A) 申请公布日期 1986.12.01
申请号 JP19850113471 申请日期 1985.05.27
申请人 MITSUBISHI ELECTRIC CORP 发明人 KISHIMOTO KAZUO
分类号 H04L7/00 主分类号 H04L7/00
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