| 摘要 |
PURPOSE:To reduce the wiring capacity by a method wherein a floating conductor layer not directly impressed with potential is provided between the first wiring conductor layer and the second wiring conductor layer. CONSTITUTION:A floating conductor 16, an upper layer wiring 15 are formed on an Si substrate 11. Assuming the parasitic capacity per unit length to be CA between the wiring 15 and the conductor 16 and CB between the conductor 16 and the substrate 11, the total parasitic capacity of wiring 15 shall be CAXCB /(CA+CB), making it feasible to reduce the parasitic capacity of wiring 15 by restricting the width of conductor 15 to 10mum or less to accelerate an IC device. |
