| 摘要 |
PURPOSE:To prevent the mis-detection of a synchronous signal by detecting the pattern of n-bit synchronous signal of a preamble part, inputting the detection signal to a counter, inputting the frequency-division output to other counter and extracting it as a synchronous signal representing the location of an effective data. CONSTITUTION:A channel data from a magnetic head 11 is inputted to a detection circuit 13 via a reproducing amplifier 12 and when the parallel output of the register and the normal synchronous signal are coincident, an output 1 is sent to an AND circuit 15 and the serial output of the shift register is fed to the synchronous pattern detection circuit 15 and its detection output is sent to the circuit 15. On the other hand, a channel clock phi is formed by a PLL16 from the data of the amplifier 12. The clock phi and an AND output P15 are inputted to a counter 17 and its carrier output and the output P15 are given to an OR circuit 18 to output a synchronous signal 18 at every 10-bit of the clock phi. A signal P18 is fed to a register 21, from which a source data is obtained from the register 21 via latches 22, 24 and a decoder 23. The outputs P15, P18 are sent to a register 31, from which a byte synchronous signal is obtained.
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