| 摘要 |
PURPOSE:To obtain a PLL circuit with a short lock time by oscillating a voltage controlled oscillator with a frequency sufficiently higher than an object frequency so as to start a frequency divider connected to the said oscillator at a specific phase of an input signal thereby controlling the initial phase of the output of the frequency divider. CONSTITUTION:The input is fed to a phase comparator circuit 4 and the input detection section 3. Then the voltage controlled oscillator VCXO1 is oscillated at a frequency being n-time of an object frequency and the output of the VCXO1 is inputted to a 1/n frequency divider 2. The output of the frequency divider 2 and the input are compared by the phase comparator 4 and its output is sent to the VCXO1 via a loop filter 5. Suppose that a phase controlled loop PLL circuit is started, a detection section 3 starts detection of the up-edge of the input signal. Then the detection section 3 generates a trigger signal starting the 1/n frequency divider 2 at the 2nd up-edge. Thus, the frequency divider 2 starts the operation and a signal with nearly matched phase is outputted after nearly a half period. |
