| 摘要 |
PURPOSE:To synchronize surely an input signal supplied asynchronously and to fetch the result by using an intermediate level detection circuit composing of two inverter circuits and a coincidence/dissidence circuit so as to detect an intermediate level of the input signal. CONSTITUTION:An input signal D from an external terminal is synchronized with an internal clock signal CK via a C-MOS inverter circuit IV1 and transmission gate MOSFETs Q1, Q2 and fetched by an output side node N1 composing of the FETs Q1, Q2. The signal from the node N1 is fed to a C-MOS inverter circuit IV3 having a comparatively high logic threshold voltage and a CMOS inverter circuit IV4 having a comparatively low logic threshold voltage. The output signal of the circuits IV3, IV4 is fed to an exclusive NOR circuit ENOR, where coincidence/dissidence of both the output levels is decided. The output of the circuit ENOR is fed to a gate of the MOSFETQ3 and when dissidence is decided, the FETQ3 is turned on and the output is pulled up to a high level. |
