发明名称 DECODING CIRCUIT
摘要 PURPOSE:To prevent the loss of capacity of a memory by providing plural error latches storing a line number of an error line, a comparator circuit, a replacement command section and an output gate so as to initialize the memory quickly. CONSTITUTION:If an error takes place in a decoder 5, an error signal ERR is sent from the decoder 5 to error latches 19, 21, 23. Then a latch 19 latches a head latch of one line from a line head latch 15 and if next error takes place, the head address is latched by the latch 21 and if next error takes place further in the latch 23. Then a comparator circuit 49 discriminates by the line number that the error line is >=1 continuous line starting from the head line of one page and a replacement command section 29 generates a replacement command signal when the line is >=1 consecutive line started from the head line. When the said signal is started, a decoded data outputted from a memory 1 is converted by an output gate 27 into, e.g., '0' and outputted.
申请公布号 JPS61269534(A) 申请公布日期 1986.11.28
申请号 JP19850111781 申请日期 1985.05.24
申请人 TOSHIBA CORP 发明人 FUSHIMI JUICHI
分类号 H03M13/00;(IPC1-7):H03M13/00 主分类号 H03M13/00
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