| 摘要 |
PURPOSE:To decrease the number of elements while minimizing static power consumption by controlling data write with a single MOS transistor (TR), using a high resistance resistive element, applying positive feedback, adjusting a logical threshold level of the 1st stage inverter and increasing the feedback resistance so as to decrease the feedback quantity. CONSTITUTION:With an input D at 'H' level, a clock CK is brought into H level to write H level to the input of the 1st inverter via a transfer gate TG 11. In this case, the 1st inverter I11 outputs L and then the 2nd inverter I12 outputs H. The output H of the 2nd inverter I12 feeds back 'H' level to the input of the 1st inverter via a feedback resistor R11. In bringing the clock CK to 'L' level, the transfer gate TG 11 is turned off to held the written data via the feedback resistor R11. When the input D is at L level 'L' is written in the input of the 1st inverter I11, the L level is fed back to hold the written data via the feedback resistor R11. |
