| 摘要 |
PURPOSE:To attain the accumulation despite of a high clock frequency or a large number of data bits to be totalized by giving an arithmetic operation in time division to each data divided in the optional bit width. CONSTITUTION:The input parallel data 1 to receive accumulation is divided into the input data 11(Xm) for upper bits and the input data 12(Xl) for lower bits and supplied to a synchronous delay circuit 13 and an accumulation unit 14 at the 1st stage. The unit 14 performs the accumulation and outputs the output 15 to the circuit 13. While an accumulation unit 17 at the 2nd stage received the input of the data Xm performs the accumulation and outputs the output 18. The circuit 13 received the output 15 outputs the accumulation result 24 of lower bits synchronously with the output timing of the unit 17. Thus the desired accumulation output 10 is obtained.
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