发明名称 ABNORMALITY PROCESSING SYSTEM IN MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To know surely the condition of a processor at detecting the abnormality by providing the exclusive-use line for stopping the processor between plural processors, detecting the abnormality by an optional processor and stopping immediately all other processors. CONSTITUTION:A program is prepared so that a processor PRS 10 may access the special memory address when the abnormality is detected, an address bus 12 to an individual memory IM11 comes to be a special pattern, this is detected by a decoder DEC 13, the pulse is generated by a timing pulse generating circuit TIM 14, a flip-flop 15 is turned on, a driver 16 is driven and a stop signal is sent to a processor stop line 17. On the other hand, the processor unit of other sub-system receives the stop signal by a receiver 18, then the unit discriminates the coincident conditions with the stop permitting signal from a DBG key 19 with a NAND 20 and indicates the stop of the processor.
申请公布号 JPS61267164(A) 申请公布日期 1986.11.26
申请号 JP19850108139 申请日期 1985.05.22
申请人 HITACHI LTD 发明人 MIYAZAKI KATSUYUKI
分类号 G06F11/30;G06F11/28;G06F15/16;G06F15/177 主分类号 G06F11/30
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